diff options
3 files changed, 402 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/qcom/vplatform-lfv-msm8996-ivi.dts b/arch/arm/boot/dts/qcom/vplatform-lfv-msm8996-ivi.dts index 54b6d0e4f132..a4532831fc1c 100644 --- a/arch/arm/boot/dts/qcom/vplatform-lfv-msm8996-ivi.dts +++ b/arch/arm/boot/dts/qcom/vplatform-lfv-msm8996-ivi.dts @@ -1,4 +1,4 @@ -/* Copyright (c) 2017, The Linux Foundation. All rights reserved. +/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -45,3 +45,14 @@ label = "ion_system_mem"; }; }; + +#include "vplatform-lfv-msm8996-usb.dtsi" + +&usb3 { + status = "okay"; + qcom,no-wakeup-src-in-hostmode; +}; + +&usb2s { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/qcom/vplatform-lfv-msm8996-telematics.dts b/arch/arm/boot/dts/qcom/vplatform-lfv-msm8996-telematics.dts index 187648f50f59..7f533292d973 100644 --- a/arch/arm/boot/dts/qcom/vplatform-lfv-msm8996-telematics.dts +++ b/arch/arm/boot/dts/qcom/vplatform-lfv-msm8996-telematics.dts @@ -167,3 +167,10 @@ status = "okay"; }; + +#include "vplatform-lfv-msm8996-usb.dtsi" + +&usb3 { + status = "okay"; + qcom,no-wakeup-src-in-hostmode; +}; diff --git a/arch/arm/boot/dts/qcom/vplatform-lfv-msm8996-usb.dtsi b/arch/arm/boot/dts/qcom/vplatform-lfv-msm8996-usb.dtsi new file mode 100644 index 000000000000..5059961e3d88 --- /dev/null +++ b/arch/arm/boot/dts/qcom/vplatform-lfv-msm8996-usb.dtsi @@ -0,0 +1,383 @@ +/* Copyright (c) 2014-2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <dt-bindings/interrupt-controller/arm-gic.h> + +&soc { + gdsc_usb30: qcom,gdsc@30f004 { + compatible = "qcom,stub-regulator"; + regulator-name = "gdsc_usb30"; + regulator-min-microvolt = <3150000>; + regulator-max-microvolt = <3600000>; + qcom,init-voltage = <3150000>; + }; + + pm8994_l24: regulator-l24 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8994_l24"; + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3075000>; + qcom,init-voltage = <3075000>; + status = "okay"; + }; + + pm8994_l28: regulator-l28 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8994_l28"; + regulator-min-microvolt = <925000>; + regulator-max-microvolt = <925000>; + qcom,init-voltage = <925000>; + proxy-supply = <&pm8994_l28>; + qcom,proxy-consumer-enable; + qcom,proxy-consumer-current = <10000>; + status = "okay"; + }; + + usb_detect: usb_detect { + compatible = "qcom,gpio-usbdetect"; + qcom,skip-vbus-detect; + }; + + usb3: ssusb@6a00000{ + compatible = "qcom,dwc-usb3-msm"; + reg = <0x06a00000 0xfc000>, + <0x07416000 0x400>; + reg-names = "core_base", + "ahb2phy_base"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + status = "disabled"; + + interrupts = <0 347 0>, <0 243 0>, <0 180 0>; + interrupt-names = "hs_phy_irq", "ss_phy_irq", "pwr_event_irq"; + + USB3_GDSC-supply = <&gdsc_usb30>; + extcon = <&usb_detect>; + qcom,usb-dbm = <&dbm_1p5>; + qcom,msm-bus,name = "usb3"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <61 512 0 0>, + <61 512 240000 800000>; + + qcom,dwc-usb3-msm-tx-fifo-size = <21288>; + + clocks = <&clock_gcc clk_gcc_usb30_master_clk>, + <&clock_gcc clk_gcc_sys_noc_usb3_axi_clk>, + <&clock_gcc clk_gcc_aggre2_usb3_axi_clk>, + <&clock_gcc clk_gcc_usb30_mock_utmi_clk>, + <&clock_gcc clk_gcc_usb30_sleep_clk>, + <&clock_gcc clk_cxo_dwc3_clk>, + <&clock_gcc clk_gcc_usb_phy_cfg_ahb2phy_clk>; + + clock-names = "core_clk", "iface_clk", "bus_aggr_clk", + "utmi_clk","sleep_clk", "xo", "cfg_ahb_clk"; + + qcom,core-clk-rate = <120000000>; + + resets = <&clock_gcc USB_30_BCR>; + reset-names = "core_reset"; + + dwc3@6a00000 { + compatible = "snps,dwc3"; + reg = <0x06a00000 0xc8d0>; + interrupts = <0 131 0>; + usb-phy = <&qusb_phy0>, <&ssphy>; + tx-fifo-resize; + snps,usb3-u1u2-disable; + snps,nominal-elastic-buffer; + snps,is-utmi-l1-suspend; + snps,hird-threshold = /bits/ 8 <0x0>; + }; + + qcom,usbbam@6b04000 { + compatible = "qcom,usb-bam-msm"; + reg = <0x06b04000 0x1a934>; + interrupts = <0 132 0>; + + qcom,bam-type = <0>; + qcom,usb-bam-fifo-baseaddr = <0x066bb000>; + qcom,usb-bam-num-pipes = <8>; + qcom,ignore-core-reset-ack; + qcom,disable-clk-gating; + qcom,usb-bam-override-threshold = <0x4001>; + qcom,usb-bam-max-mbps-highspeed = <400>; + qcom,usb-bam-max-mbps-superspeed = <3600>; + qcom,reset-bam-on-connect; + + qcom,pipe0 { + label = "ssusb-ipa-out-0"; + qcom,usb-bam-mem-type = <1>; + qcom,dir = <0>; + qcom,pipe-num = <0>; + qcom,peer-bam = <1>; + qcom,src-bam-pipe-index = <1>; + qcom,data-fifo-size = <0x8000>; + qcom,descriptor-fifo-size = <0x2000>; + }; + qcom,pipe1 { + label = "ssusb-ipa-in-0"; + qcom,usb-bam-mem-type = <1>; + qcom,dir = <1>; + qcom,pipe-num = <0>; + qcom,peer-bam = <1>; + qcom,dst-bam-pipe-index = <0>; + qcom,data-fifo-size = <0x8000>; + qcom,descriptor-fifo-size = <0x2000>; + }; + qcom,pipe2 { + label = "ssusb-qdss-in-0"; + qcom,usb-bam-mem-type = <2>; + qcom,dir = <1>; + qcom,pipe-num = <0>; + qcom,peer-bam = <0>; + qcom,peer-bam-physical-address = <0x03084000>; + qcom,src-bam-pipe-index = <0>; + qcom,dst-bam-pipe-index = <2>; + qcom,data-fifo-offset = <0x0>; + qcom,data-fifo-size = <0x1800>; + qcom,descriptor-fifo-offset = <0x1800>; + qcom,descriptor-fifo-size = <0x800>; + }; + qcom,pipe3 { + label = "ssusb-dpl-ipa-in-1"; + qcom,usb-bam-mem-type = <1>; + qcom,dir = <1>; + qcom,pipe-num = <1>; + qcom,peer-bam = <1>; + qcom,dst-bam-pipe-index = <2>; + qcom,data-fifo-size = <0x8000>; + qcom,descriptor-fifo-size = <0x2000>; + }; + }; + }; + + usb2s: hsusb@7600000 { + compatible = "qcom,dwc-usb3-msm"; + reg = <0x07600000 0xfc000>, + <0x7416000 0x400>; + reg-names = "core_base", + "ahb2phy_base"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + status = "disabled"; + + interrupts = <0 352 0>, <0 140 0>; + interrupt-names = "hs_phy_irq", "pwr_event_irq"; + + qcom,msm-bus,name = "usb-hs"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <87 512 0 0>, + <87 512 60000 960000>; + + clocks = <&clock_gcc clk_gcc_usb20_master_clk>, + <&clock_gcc clk_gcc_periph_noc_usb20_ahb_clk>, + <&clock_gcc clk_gcc_usb20_mock_utmi_clk>, + <&clock_gcc clk_gcc_usb20_sleep_clk>, + <&clock_gcc clk_cxo_dwc3_clk>, + <&clock_gcc clk_gcc_usb_phy_cfg_ahb2phy_clk>; + clock-names = "core_clk", "iface_clk", "utmi_clk", "sleep_clk", + "xo", "cfg_ahb_clk"; + qcom,core-clk-rate = <60000000>; + resets = <&clock_gcc USB_20_BCR>; + reset-names = "core_reset"; + qcom,disable-host-mode-pm; + + dwc3@7600000 { + compatible = "snps,dwc3"; + reg = <0x07600000 0xc8d0>; + interrupts = <0 138 0>; + usb-phy = <&qusb_phy1>, <&usb_nop_phy>; + maximum-speed = "high-speed"; + snps,nominal-elastic-buffer; + snps,is-utmi-l1-suspend; + snps,hird-threshold = /bits/ 8 <0x0>; + }; + }; + + qusb_phy0: qusb@7411000 { + compatible = "qcom,qusb2phy"; + reg = <0x07411000 0x180>, + <0x0007024c 0x4>, + <0x00388018 0x4>; + reg-names = "qusb_phy_base", + "tune2_efuse_addr", + "ref_clk_addr"; + vdd-supply = <&pm8994_s2_corner>; + vdda18-supply = <&pm8994_l12>; + vdda33-supply = <&pm8994_l24>; + qcom,vdd-voltage-level = <1 5 7>; + qcom,tune2-efuse-bit-pos = <21>; + qcom,tune2-efuse-num-bits = <4>; + qcom,qusb-phy-init-seq = <0xF8 0x80 + 0xB3 0x84 + 0x83 0x88 + 0xC0 0x8C + 0x30 0x08 + 0x79 0x0C + 0x21 0x10 + 0x14 0x9C + 0x9F 0x1C + 0x00 0x18>; + phy_type= "utmi"; + qcom,phy-clk-scheme = "cmos"; + qcom,major-rev = <1>; + + clocks = <&clock_gcc clk_gcc_usb_phy_cfg_ahb2phy_clk>, + <&clock_gcc clk_ln_bb_clk>; + clock-names = "cfg_ahb_clk", "ref_clk_src"; + + resets = <&clock_gcc QUSB2PHY_PRIM_BCR>; + reset-names = "phy_reset"; + }; + + qusb_phy1: qusb@7412000 { + compatible = "qcom,qusb2phy"; + reg = <0x07412000 0x180>, + <0x0007024c 0x4>, + <0x00388014 0x4>; + reg-names = "qusb_phy_base", + "tune2_efuse_addr", + "ref_clk_addr"; + vdd-supply = <&pm8994_s2_corner>; + vdda18-supply = <&pm8994_l12>; + vdda33-supply = <&pm8994_l24>; + qcom,vdd-voltage-level = <1 5 7>; + qcom,tune2-efuse-bit-pos = <25>; + qcom,tune2-efuse-num-bits = <4>; + qcom,qusb-phy-init-seq = <0xF8 0x80 + 0xB3 0x84 + 0x83 0x88 + 0xC0 0x8C + 0x30 0x08 + 0x79 0x0C + 0x21 0x10 + 0x14 0x9C + 0x9F 0x1C + 0x00 0x18>; + phy_type = "utmi"; + qcom,phy-clk-scheme = "cmos"; + qcom,major-rev = <1>; + qcom,hold-reset; + + clocks = <&clock_gcc clk_gcc_usb_phy_cfg_ahb2phy_clk>, + <&clock_gcc clk_ln_bb_clk>; + clock-names = "cfg_ahb_clk", "ref_clk_src"; + + resets = <&clock_gcc QUSB2PHY_SEC_BCR>; + reset-names = "phy_reset"; + }; + + ssphy: ssphy@7410000 { + compatible = "qcom,usb-ssphy-qmp-v2"; + reg = <0x07410000 0x7a8>; + reg-names = "qmp_phy_base"; + vdd-supply = <&pm8994_l28>; + core-supply = <&pm8994_l12>; + qcom,core-voltage-level = <0 1800000 1800000>; + qcom,vdd-voltage-level = <0 925000 925000>; + qcom,vbus-valid-override; + qcom,qmp-phy-init-seq = + /* <reg_offset, value, delay> */ + <0xac 0x14 0x00 /* common block settings */ + 0x34 0x08 0x00 + 0x174 0x30 0x00 + 0x194 0x06 0x00 + 0x19c 0x01 0x00 + 0x178 0x00 0x00 + 0x70 0x0f 0x00 + 0x48 0x0f 0x00 + 0x3c 0x04 0x00 + 0xd0 0x82 0x00/* pll, loop filter settings*/ + 0xdc 0x55 0x00 + 0xe0 0x55 0x00 + 0xe4 0x03 0x00 + 0x78 0x0b 0x00 + 0x84 0x16 0x00 + 0x90 0x28 0x00 + 0x108 0x80 0x00 + 0x124 0x00 0x00 + 0x4c 0x15 0x00 + 0x50 0x34 0x00 + 0x18c 0x00 0x00 + 0xcc 0x00 0x00 + 0x128 0x00 0x00 + 0x0c 0x0a 0x00 + 0x10 0x01 0x00 /* ssc settings */ + 0x1c 0x31 0x00 + 0x20 0x01 0x00 + 0x14 0x00 0x00 + 0x18 0x00 0x00 + 0x24 0xde 0x00 + 0x28 0x07 0x00 + 0x440 0x0b 0x00 /* Rx settings */ + 0x41c 0x04 0x00 + 0x4d8 0x02 0x00 + 0x4dc 0x4c 0x00 + 0x4e0 0xbb 0x00 + 0x508 0x77 0x00 + 0x50c 0x80 0x00 + 0x514 0x03 0x00 + 0x518 0x18 0x00 + 0x51c 0x16 0x00 + 0x268 0x45 0x00 /* Tx settings */ + 0x2ac 0x12 0x00 + 0x294 0x06 0x00 + 0x6c4 0x03 0x00 /* FLL settings */ + 0x6c0 0x02 0x00 + 0x6c8 0x09 0x00 + 0x6cc 0x42 0x00 + 0x6d0 0x85 0x00 + 0x680 0xd1 0x00 /* Lock Det settings */ + 0x684 0x1f 0x00 + 0x688 0x47 0x00 + 0x664 0x08 0x00 + 0xffffffff 0xffffffff 0x00>; + + qcom,qmp-phy-reg-offset = + <0x77c /* USB3_PHY_PCS_STATUS */ + 0x6d4 /* USB3_PHY_AUTONOMOUS_MODE_CTRL */ + 0x6d8 /* USB3_PHY_LFPS_RXTERM_IRQ_CLEAR */ + 0x604 /* USB3_PHY_POWER_DOWN_CONTROL */ + 0x600 /* USB3_PHY_SW_RESET */ + 0x608>; /* USB3_PHY_START */ + + clocks = <&clock_gcc clk_gcc_usb3_phy_aux_clk>, + <&clock_gcc clk_gcc_usb3_phy_pipe_clk>, + <&clock_gcc clk_gcc_usb_phy_cfg_ahb2phy_clk>, + <&clock_gcc clk_ln_bb_clk>, + <&clock_gcc clk_gcc_usb3_clkref_clk>; + + clock-names = "aux_clk", "pipe_clk", "cfg_ahb_clk", + "ref_clk_src", "ref_clk"; + + resets = <&clock_gcc USB3_PHY_BCR>, + <&clock_gcc USB3PHY_PHY_BCR>; + reset-names = "phy_reset", "phy_phy_reset"; + qcom,disable-autonomous-mode; + }; + + usb_nop_phy: usb_nop_phy { + compatible = "usb-nop-xceiv"; + }; + + dbm_1p5: dbm@6af8000 { + compatible = "qcom,usb-dbm-1p5"; + reg = <0x06af8000 0x300>; + qcom,reset-ep-after-lpm-resume; + }; +}; |