diff options
| -rw-r--r-- | drivers/clk/qcom/gcc-sdm660.c | 9 | ||||
| -rw-r--r-- | drivers/clk/qcom/mmcc-sdm660.c | 42 |
2 files changed, 51 insertions, 0 deletions
diff --git a/drivers/clk/qcom/gcc-sdm660.c b/drivers/clk/qcom/gcc-sdm660.c index b10f9ca9fe1a..251acafca196 100644 --- a/drivers/clk/qcom/gcc-sdm660.c +++ b/drivers/clk/qcom/gcc-sdm660.c @@ -2958,6 +2958,9 @@ static const char *const debug_mux_parent_names[] = { "mmss_video_axi_clk", "mmss_video_core_clk", "mmss_video_subcore0_clk", + "mmss_throttle_camss_axi_clk", + "mmss_throttle_mdss_axi_clk", + "mmss_throttle_video_axi_clk", "gpucc_gfx3d_clk", "gpucc_rbbmtimer_clk", "gpucc_rbcpr_clk", @@ -3223,6 +3226,12 @@ static struct clk_debug_mux gcc_debug_mux = { 0x00E, 0, 0, 0x1000, BM(14, 13) }, { "mmss_video_subcore0_clk", 0x22, MMCC, 0x01A, 0, 0, 0x1000, BM(14, 13) }, + { "mmss_throttle_camss_axi_clk", 0x22, MMCC, + 0x0AA, 0, 0, 0x1000, BM(14, 13) }, + { "mmss_throttle_mdss_axi_clk", 0x22, MMCC, + 0x0AB, 0, 0, 0x1000, BM(14, 13) }, + { "mmss_throttle_video_axi_clk", 0x22, MMCC, + 0x0AC, 0, 0, 0x1000, BM(14, 13) }, { "gpucc_gfx3d_clk", 0x13d, GPU, 0x008, 0, 0, 0, BM(18, 17) }, { "gpucc_rbbmtimer_clk", 0x13d, GPU, diff --git a/drivers/clk/qcom/mmcc-sdm660.c b/drivers/clk/qcom/mmcc-sdm660.c index 910c36c65b6a..542737e4d204 100644 --- a/drivers/clk/qcom/mmcc-sdm660.c +++ b/drivers/clk/qcom/mmcc-sdm660.c @@ -2053,6 +2053,19 @@ static struct clk_branch mmss_camss_jpeg_axi_clk = { }, }; +static struct clk_branch mmss_throttle_camss_axi_clk = { + .halt_reg = 0x3c3c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x3c3c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_throttle_camss_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_branch mmss_camss_mclk0_clk = { .halt_reg = 0x3384, .halt_check = BRANCH_HALT, @@ -2341,6 +2354,19 @@ static struct clk_branch mmss_mdss_axi_clk = { }, }; +static struct clk_branch mmss_throttle_mdss_axi_clk = { + .halt_reg = 0x246c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x246c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_throttle_mdss_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_branch mmss_mdss_byte0_clk = { .halt_reg = 0x233c, .halt_check = BRANCH_HALT, @@ -2801,6 +2827,19 @@ static struct clk_branch mmss_video_axi_clk = { }, }; +static struct clk_branch mmss_throttle_video_axi_clk = { + .halt_reg = 0x118c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x118c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_throttle_video_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_branch mmss_video_core_clk = { .halt_reg = 0x1028, .halt_check = BRANCH_HALT, @@ -2962,6 +3001,9 @@ static struct clk_regmap *mmcc_660_clocks[] = { [MMSS_MISC_CXO_CLK] = &mmss_misc_cxo_clk.clkr, [MMSS_MNOC_AHB_CLK] = &mmss_mnoc_ahb_clk.clkr, [MMSS_SNOC_DVM_AXI_CLK] = &mmss_snoc_dvm_axi_clk.clkr, + [MMSS_THROTTLE_CAMSS_AXI_CLK] = &mmss_throttle_camss_axi_clk.clkr, + [MMSS_THROTTLE_MDSS_AXI_CLK] = &mmss_throttle_mdss_axi_clk.clkr, + [MMSS_THROTTLE_VIDEO_AXI_CLK] = &mmss_throttle_video_axi_clk.clkr, [MMSS_VIDEO_AHB_CLK] = &mmss_video_ahb_clk.clkr, [MMSS_VIDEO_AXI_CLK] = &mmss_video_axi_clk.clkr, [MMSS_VIDEO_CORE_CLK] = &mmss_video_core_clk.clkr, |