Merge branch 'perf/core' into perf/uprobes

Merge in latest upstream (and the latest perf development tree),
to prepare for tooling changes, and also to pick up v3.4 MM
changes that the uprobes code needs to take care of.

Signed-off-by: Ingo Molnar <mingo@kernel.org>

1 files changed, 104 insertions, 105 deletions

diff --git a/drivers/isdn/hisax/jade.c b/drivers/isdn/hisax/jade.c
index a06cea09158b..f946c58d8ab1 100644
--- a/drivers/isdn/hisax/jade.c
+++ b/drivers/isdn/hisax/jade.c
@@ -4,7 +4,7 @@
  *
  * Author       Roland Klabunde
  * Copyright    by Roland Klabunde   <R.Klabunde@Berkom.de>
- * 
+ *
  * This software may be used and distributed according to the terms
  * of the GNU General Public License, incorporated herein by reference.
  *
@@ -23,53 +23,53 @@
 int
 JadeVersion(struct IsdnCardState *cs, char *s)
 {
-    int ver;
-    int to = 50;
-    cs->BC_Write_Reg(cs, -1, 0x50, 0x19);
-    while (to) {
-    	udelay(1);
+	int ver;
+	int to = 50;
+	cs->BC_Write_Reg(cs, -1, 0x50, 0x19);
+	while (to) {
+		udelay(1);
+		ver = cs->BC_Read_Reg(cs, -1, 0x60);
+		to--;
+		if (ver)
+			break;
+		if (!to) {
+			printk(KERN_INFO "%s JADE version not obtainable\n", s);
+			return (0);
+		}
+	}
+	/* Wait for the JADE */
+	udelay(10);
+	/* Read version */
 	ver = cs->BC_Read_Reg(cs, -1, 0x60);
-	to--;
-	if (ver)
-    	    break;
-	if (!to) {
-	    printk(KERN_INFO "%s JADE version not obtainable\n", s);
-    	    return (0);
-        }
-    }
-    /* Wait for the JADE */
-    udelay(10);
-    /* Read version */
-    ver = cs->BC_Read_Reg(cs, -1, 0x60);
-    printk(KERN_INFO "%s JADE version: %d\n", s, ver);
-    return (1);
+	printk(KERN_INFO "%s JADE version: %d\n", s, ver);
+	return (1);
 }
 
 /* Write to indirect accessible jade register set */
 static void
 jade_write_indirect(struct IsdnCardState *cs, u_char reg, u_char value)
 {
-    int to = 50;
-    u_char ret;
+	int to = 50;
+	u_char ret;
 
-    /* Write the data */
-    cs->BC_Write_Reg(cs, -1, COMM_JADE+1, value);
-    /* Say JADE we wanna write indirect reg 'reg' */
-    cs->BC_Write_Reg(cs, -1, COMM_JADE, reg);
-    to = 50;
-    /* Wait for RDY goes high */
-    while (to) {
-    	udelay(1);
-	ret = cs->BC_Read_Reg(cs, -1, COMM_JADE);
-	to--;
-	if (ret & 1)
-	    /* Got acknowledge */
-	    break;
-	if (!to) {
-    	    printk(KERN_INFO "Can not see ready bit from JADE DSP (reg=0x%X, value=0x%X)\n", reg, value);
-	    return;
+	/* Write the data */
+	cs->BC_Write_Reg(cs, -1, COMM_JADE + 1, value);
+	/* Say JADE we wanna write indirect reg 'reg' */
+	cs->BC_Write_Reg(cs, -1, COMM_JADE, reg);
+	to = 50;
+	/* Wait for RDY goes high */
+	while (to) {
+		udelay(1);
+		ret = cs->BC_Read_Reg(cs, -1, COMM_JADE);
+		to--;
+		if (ret & 1)
+			/* Got acknowledge */
+			break;
+		if (!to) {
+			printk(KERN_INFO "Can not see ready bit from JADE DSP (reg=0x%X, value=0x%X)\n", reg, value);
+			return;
+		}
 	}
-    }
 }
 
 
@@ -77,67 +77,67 @@ jade_write_indirect(struct IsdnCardState *cs, u_char reg, u_char value)
 static void
 modejade(struct BCState *bcs, int mode, int bc)
 {
-    struct IsdnCardState *cs = bcs->cs;
-    int jade = bcs->hw.hscx.hscx;
+	struct IsdnCardState *cs = bcs->cs;
+	int jade = bcs->hw.hscx.hscx;
 
-    if (cs->debug & L1_DEB_HSCX) {
-	char tmp[40];
-	sprintf(tmp, "jade %c mode %d ichan %d",
-		'A' + jade, mode, bc);
-	debugl1(cs, tmp);
-    }
-    bcs->mode = mode;
-    bcs->channel = bc;
-	
-    cs->BC_Write_Reg(cs, jade, jade_HDLC_MODE, (mode == L1_MODE_TRANS ? jadeMODE_TMO:0x00));
-    cs->BC_Write_Reg(cs, jade, jade_HDLC_CCR0, (jadeCCR0_PU|jadeCCR0_ITF));
-    cs->BC_Write_Reg(cs, jade, jade_HDLC_CCR1, 0x00);
+	if (cs->debug & L1_DEB_HSCX) {
+		char tmp[40];
+		sprintf(tmp, "jade %c mode %d ichan %d",
+			'A' + jade, mode, bc);
+		debugl1(cs, tmp);
+	}
+	bcs->mode = mode;
+	bcs->channel = bc;
 
-    jade_write_indirect(cs, jade_HDLC1SERRXPATH, 0x08);
-    jade_write_indirect(cs, jade_HDLC2SERRXPATH, 0x08);
-    jade_write_indirect(cs, jade_HDLC1SERTXPATH, 0x00);
-    jade_write_indirect(cs, jade_HDLC2SERTXPATH, 0x00);
+	cs->BC_Write_Reg(cs, jade, jade_HDLC_MODE, (mode == L1_MODE_TRANS ? jadeMODE_TMO : 0x00));
+	cs->BC_Write_Reg(cs, jade, jade_HDLC_CCR0, (jadeCCR0_PU | jadeCCR0_ITF));
+	cs->BC_Write_Reg(cs, jade, jade_HDLC_CCR1, 0x00);
 
-    cs->BC_Write_Reg(cs, jade, jade_HDLC_XCCR, 0x07);
-    cs->BC_Write_Reg(cs, jade, jade_HDLC_RCCR, 0x07);
+	jade_write_indirect(cs, jade_HDLC1SERRXPATH, 0x08);
+	jade_write_indirect(cs, jade_HDLC2SERRXPATH, 0x08);
+	jade_write_indirect(cs, jade_HDLC1SERTXPATH, 0x00);
+	jade_write_indirect(cs, jade_HDLC2SERTXPATH, 0x00);
 
-    if (bc == 0) {
-	cs->BC_Write_Reg(cs, jade, jade_HDLC_TSAX, 0x00);
-	cs->BC_Write_Reg(cs, jade, jade_HDLC_TSAR, 0x00);
-    } else {
-	cs->BC_Write_Reg(cs, jade, jade_HDLC_TSAX, 0x04);
-	cs->BC_Write_Reg(cs, jade, jade_HDLC_TSAR, 0x04);
-    }
-    switch (mode) {
+	cs->BC_Write_Reg(cs, jade, jade_HDLC_XCCR, 0x07);
+	cs->BC_Write_Reg(cs, jade, jade_HDLC_RCCR, 0x07);
+
+	if (bc == 0) {
+		cs->BC_Write_Reg(cs, jade, jade_HDLC_TSAX, 0x00);
+		cs->BC_Write_Reg(cs, jade, jade_HDLC_TSAR, 0x00);
+	} else {
+		cs->BC_Write_Reg(cs, jade, jade_HDLC_TSAX, 0x04);
+		cs->BC_Write_Reg(cs, jade, jade_HDLC_TSAR, 0x04);
+	}
+	switch (mode) {
 	case (L1_MODE_NULL):
 		cs->BC_Write_Reg(cs, jade, jade_HDLC_MODE, jadeMODE_TMO);
 		break;
 	case (L1_MODE_TRANS):
-		cs->BC_Write_Reg(cs, jade, jade_HDLC_MODE, (jadeMODE_TMO|jadeMODE_RAC|jadeMODE_XAC));
+		cs->BC_Write_Reg(cs, jade, jade_HDLC_MODE, (jadeMODE_TMO | jadeMODE_RAC | jadeMODE_XAC));
 		break;
 	case (L1_MODE_HDLC):
-		cs->BC_Write_Reg(cs, jade, jade_HDLC_MODE, (jadeMODE_RAC|jadeMODE_XAC));
+		cs->BC_Write_Reg(cs, jade, jade_HDLC_MODE, (jadeMODE_RAC | jadeMODE_XAC));
 		break;
-    }
-    if (mode) {
-	cs->BC_Write_Reg(cs, jade, jade_HDLC_RCMD, (jadeRCMD_RRES|jadeRCMD_RMC));
-	cs->BC_Write_Reg(cs, jade, jade_HDLC_XCMD, jadeXCMD_XRES);
-	/* Unmask ints */
-	cs->BC_Write_Reg(cs, jade, jade_HDLC_IMR, 0xF8);
-    }
-    else
-	/* Mask ints */
-	cs->BC_Write_Reg(cs, jade, jade_HDLC_IMR, 0x00);
+	}
+	if (mode) {
+		cs->BC_Write_Reg(cs, jade, jade_HDLC_RCMD, (jadeRCMD_RRES | jadeRCMD_RMC));
+		cs->BC_Write_Reg(cs, jade, jade_HDLC_XCMD, jadeXCMD_XRES);
+		/* Unmask ints */
+		cs->BC_Write_Reg(cs, jade, jade_HDLC_IMR, 0xF8);
+	}
+	else
+		/* Mask ints */
+		cs->BC_Write_Reg(cs, jade, jade_HDLC_IMR, 0x00);
 }
 
 static void
 jade_l2l1(struct PStack *st, int pr, void *arg)
 {
-    struct BCState *bcs = st->l1.bcs;
-    struct sk_buff *skb = arg;
-    u_long flags;
+	struct BCState *bcs = st->l1.bcs;
+	struct sk_buff *skb = arg;
+	u_long flags;
 
-    switch (pr) {
+	switch (pr) {
 	case (PH_DATA | REQUEST):
 		spin_lock_irqsave(&bcs->cs->lock, flags);
 		if (bcs->tx_skb) {
@@ -164,10 +164,10 @@ jade_l2l1(struct PStack *st, int pr, void *arg)
 		break;
 	case (PH_PULL | REQUEST):
 		if (!bcs->tx_skb) {
-		    test_and_clear_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
-		    st->l1.l1l2(st, PH_PULL | CONFIRM, NULL);
+			test_and_clear_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
+			st->l1.l1l2(st, PH_PULL | CONFIRM, NULL);
 		} else
-		    test_and_set_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
+			test_and_set_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
 		break;
 	case (PH_ACTIVATE | REQUEST):
 		spin_lock_irqsave(&bcs->cs->lock, flags);
@@ -187,26 +187,26 @@ jade_l2l1(struct PStack *st, int pr, void *arg)
 		spin_unlock_irqrestore(&bcs->cs->lock, flags);
 		st->l1.l1l2(st, PH_DEACTIVATE | CONFIRM, NULL);
 		break;
-    }
+	}
 }
 
 static void
 close_jadestate(struct BCState *bcs)
 {
-    modejade(bcs, 0, bcs->channel);
-    if (test_and_clear_bit(BC_FLG_INIT, &bcs->Flag)) {
-	kfree(bcs->hw.hscx.rcvbuf);
-	bcs->hw.hscx.rcvbuf = NULL;
-	kfree(bcs->blog);
-	bcs->blog = NULL;
-	skb_queue_purge(&bcs->rqueue);
-	skb_queue_purge(&bcs->squeue);
-	if (bcs->tx_skb) {
-		dev_kfree_skb_any(bcs->tx_skb);
-		bcs->tx_skb = NULL;
-		test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
+	modejade(bcs, 0, bcs->channel);
+	if (test_and_clear_bit(BC_FLG_INIT, &bcs->Flag)) {
+		kfree(bcs->hw.hscx.rcvbuf);
+		bcs->hw.hscx.rcvbuf = NULL;
+		kfree(bcs->blog);
+		bcs->blog = NULL;
+		skb_queue_purge(&bcs->rqueue);
+		skb_queue_purge(&bcs->squeue);
+		if (bcs->tx_skb) {
+			dev_kfree_skb_any(bcs->tx_skb);
+			bcs->tx_skb = NULL;
+			test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
+		}
 	}
-    }
 }
 
 static int
@@ -221,7 +221,7 @@ open_jadestate(struct IsdnCardState *cs, struct BCState *bcs)
 		}
 		if (!(bcs->blog = kmalloc(MAX_BLOG_SPACE, GFP_ATOMIC))) {
 			printk(KERN_WARNING
-				"HiSax: No memory for bcs->blog\n");
+			       "HiSax: No memory for bcs->blog\n");
 			test_and_clear_bit(BC_FLG_INIT, &bcs->Flag);
 			kfree(bcs->hw.hscx.rcvbuf);
 			bcs->hw.hscx.rcvbuf = NULL;
@@ -303,12 +303,11 @@ initjade(struct IsdnCardState *cs)
 	cs->BC_Write_Reg(cs, 0, jade_HDLC_IMR,  0x00);
 	cs->BC_Write_Reg(cs, 1, jade_HDLC_IMR,  0x00);
 	/* Setup host access to hdlc controller */
-	jade_write_indirect(cs, jade_HDLCCNTRACCESS, (jadeINDIRECT_HAH1|jadeINDIRECT_HAH2));
+	jade_write_indirect(cs, jade_HDLCCNTRACCESS, (jadeINDIRECT_HAH1 | jadeINDIRECT_HAH2));
 	/* Unmask HDLC int (don't forget DSP int later on)*/
-	cs->BC_Write_Reg(cs, -1,jade_INT, (jadeINT_HDLC1|jadeINT_HDLC2));
+	cs->BC_Write_Reg(cs, -1, jade_INT, (jadeINT_HDLC1 | jadeINT_HDLC2));
 
-	/* once again TRANSPARENT */	
+	/* once again TRANSPARENT */
 	modejade(cs->bcs, 0, 0);
 	modejade(cs->bcs + 1, 0, 0);
 }
-