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authorGreg Kroah-Hartman <gregkh@linuxfoundation.org>2014-02-24 13:33:45 -0800
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2014-02-24 13:33:45 -0800
commit35efc5a425e3db676b3d1ab9f23705a3977cfdcd (patch)
tree5dd2f9211b17eaad73f09bdc80172bea7dbb0760 /drivers/gpu/drm/i915/intel_display.c
parent0a191749ce19112f8f20675232b951dccd4ae00e (diff)
parentcfbf8d4857c26a8a307fb7cd258074c9dcd8c691 (diff)
Merge 3.14-rc4 into char-misc-next
We want these fixes here as well. Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_display.c')
-rw-r--r--drivers/gpu/drm/i915/intel_display.c14
1 files changed, 14 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 9fa24347963a..4c1672809493 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -8586,6 +8586,20 @@ static int intel_gen7_queue_flip(struct drm_device *dev,
if (ring->id == RCS)
len += 6;
+ /*
+ * BSpec MI_DISPLAY_FLIP for IVB:
+ * "The full packet must be contained within the same cache line."
+ *
+ * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
+ * cacheline, if we ever start emitting more commands before
+ * the MI_DISPLAY_FLIP we may need to first emit everything else,
+ * then do the cacheline alignment, and finally emit the
+ * MI_DISPLAY_FLIP.
+ */
+ ret = intel_ring_cacheline_align(ring);
+ if (ret)
+ goto err_unpin;
+
ret = intel_ring_begin(ring, len);
if (ret)
goto err_unpin;