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| author | Ingo Molnar <mingo@elte.hu> | 2008-11-10 09:10:44 +0100 |
|---|---|---|
| committer | Ingo Molnar <mingo@elte.hu> | 2008-11-10 09:10:44 +0100 |
| commit | a5a64498c194c82ecad3a2d67cff6231cda8d3dd (patch) | |
| tree | 723d5d81419f9960b8d30ed9a2ece8a58d6c4328 /arch/parisc/include/asm/prefetch.h | |
| parent | bb93d802ae5c1949977cc6da247b218240677f11 (diff) | |
| parent | f7160c7573615ec82c691e294cf80d920b5d588d (diff) | |
Merge commit 'v2.6.28-rc4' into timers/rtc
Conflicts:
drivers/rtc/rtc-cmos.c
Diffstat (limited to 'arch/parisc/include/asm/prefetch.h')
| -rw-r--r-- | arch/parisc/include/asm/prefetch.h | 39 |
1 files changed, 39 insertions, 0 deletions
diff --git a/arch/parisc/include/asm/prefetch.h b/arch/parisc/include/asm/prefetch.h new file mode 100644 index 000000000000..c5edc60c059f --- /dev/null +++ b/arch/parisc/include/asm/prefetch.h @@ -0,0 +1,39 @@ +/* + * include/asm-parisc/prefetch.h + * + * PA 2.0 defines data prefetch instructions on page 6-11 of the Kane book. + * In addition, many implementations do hardware prefetching of both + * instructions and data. + * + * PA7300LC (page 14-4 of the ERS) also implements prefetching by a load + * to gr0 but not in a way that Linux can use. If the load would cause an + * interruption (eg due to prefetching 0), it is suppressed on PA2.0 + * processors, but not on 7300LC. + * + */ + +#ifndef __ASM_PARISC_PREFETCH_H +#define __ASM_PARISC_PREFETCH_H + +#ifndef __ASSEMBLY__ +#ifdef CONFIG_PREFETCH + +#define ARCH_HAS_PREFETCH +static inline void prefetch(const void *addr) +{ + __asm__("ldw 0(%0), %%r0" : : "r" (addr)); +} + +/* LDD is a PA2.0 addition. */ +#ifdef CONFIG_PA20 +#define ARCH_HAS_PREFETCHW +static inline void prefetchw(const void *addr) +{ + __asm__("ldd 0(%0), %%r0" : : "r" (addr)); +} +#endif /* CONFIG_PA20 */ + +#endif /* CONFIG_PREFETCH */ +#endif /* __ASSEMBLY__ */ + +#endif /* __ASM_PARISC_PROCESSOR_H */ |
