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| author | Xiaowen Wu <wxiaowen@codeaurora.org> | 2019-03-13 18:10:04 -0400 |
|---|---|---|
| committer | Gerrit - the friendly Code Review server <code-review@localhost> | 2019-03-27 22:04:52 -0700 |
| commit | af3c1903749cb0d7c40eff82f4fd12cc102dbe0b (patch) | |
| tree | 527082ee0f726bbc593040e9ad2936af8c997acc /arch/mips/kernel/irq.c | |
| parent | bff3c3db6b1171211b87d15530312acbc2e650fd (diff) | |
drm/msm/sde: add post_disable stage for phys encoder
add post_disable stage for each phys encoder to clear ctl_top
Change-Id: Ib34059546b6ddf7bbd2c60fd8321a7f820b97986
Signed-off-by: Xiaowen Wu <wxiaowen@codeaurora.org>
Diffstat (limited to 'arch/mips/kernel/irq.c')
0 files changed, 0 insertions, 0 deletions