diff options
| author | Paul Moore <pmoore@redhat.com> | 2014-06-17 17:30:23 -0400 |
|---|---|---|
| committer | Paul Moore <pmoore@redhat.com> | 2014-06-17 17:30:23 -0400 |
| commit | 170b5910d9fbea79de1bb40df22eda5f98250c0c (patch) | |
| tree | ca9560e878d2842d45c6f99077d0d8b8f8b0f9ba /arch/arm/mach-omap2/clkt_dpll.c | |
| parent | 47dd0b76ace953bd2c0479076db0d3e3b9594003 (diff) | |
| parent | 1860e379875dfe7271c649058aeddffe5afd9d0d (diff) | |
Merge tag 'v3.15' into next
Linux 3.15
Diffstat (limited to 'arch/arm/mach-omap2/clkt_dpll.c')
| -rw-r--r-- | arch/arm/mach-omap2/clkt_dpll.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/arch/arm/mach-omap2/clkt_dpll.c b/arch/arm/mach-omap2/clkt_dpll.c index 47f9562ca7aa..332af927f4d3 100644 --- a/arch/arm/mach-omap2/clkt_dpll.c +++ b/arch/arm/mach-omap2/clkt_dpll.c @@ -209,7 +209,7 @@ u8 omap2_init_dpll_parent(struct clk_hw *hw) if (v == OMAP3XXX_EN_DPLL_LPBYPASS || v == OMAP3XXX_EN_DPLL_FRBYPASS) return 1; - } else if (soc_is_am33xx() || cpu_is_omap44xx()) { + } else if (soc_is_am33xx() || cpu_is_omap44xx() || soc_is_am43xx()) { if (v == OMAP4XXX_EN_DPLL_LPBYPASS || v == OMAP4XXX_EN_DPLL_FRBYPASS || v == OMAP4XXX_EN_DPLL_MNBYPASS) @@ -255,7 +255,7 @@ unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk) if (v == OMAP3XXX_EN_DPLL_LPBYPASS || v == OMAP3XXX_EN_DPLL_FRBYPASS) return __clk_get_rate(dd->clk_bypass); - } else if (soc_is_am33xx() || cpu_is_omap44xx()) { + } else if (soc_is_am33xx() || cpu_is_omap44xx() || soc_is_am43xx()) { if (v == OMAP4XXX_EN_DPLL_LPBYPASS || v == OMAP4XXX_EN_DPLL_FRBYPASS || v == OMAP4XXX_EN_DPLL_MNBYPASS) @@ -306,7 +306,7 @@ long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate, ref_rate = __clk_get_rate(dd->clk_ref); clk_name = __clk_get_name(hw->clk); - pr_debug("clock: %s: starting DPLL round_rate, target rate %ld\n", + pr_debug("clock: %s: starting DPLL round_rate, target rate %lu\n", clk_name, target_rate); scaled_rt_rp = target_rate / (ref_rate / DPLL_SCALE_FACTOR); @@ -342,7 +342,7 @@ long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate, if (r == DPLL_MULT_UNDERFLOW) continue; - pr_debug("clock: %s: m = %d: n = %d: new_rate = %ld\n", + pr_debug("clock: %s: m = %d: n = %d: new_rate = %lu\n", clk_name, m, n, new_rate); if (target_rate == new_rate) { @@ -354,7 +354,7 @@ long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate, } if (target_rate != new_rate) { - pr_debug("clock: %s: cannot round to rate %ld\n", + pr_debug("clock: %s: cannot round to rate %lu\n", clk_name, target_rate); return ~0; } |