diff options
| author | Taniya Das <tdas@codeaurora.org> | 2017-02-06 15:52:25 +0530 |
|---|---|---|
| committer | Taniya Das <tdas@codeaurora.org> | 2017-02-07 12:08:51 +0530 |
| commit | 0b6b50f4e47346c31a27776fbe30c0b2d573925c (patch) | |
| tree | b098a39a33c1b5c669b8b9f44f634f5466bcb7f7 | |
| parent | 038297471d2ab1dcdc637d29ab916b44d38ced2e (diff) | |
clk: qcom: Update the dp pixel clock flags
Display port pixel clock source is required to propagate the set rate to
parent, so update the flags for the same. The lowsvs frequency has got
updated to 154MHz, update the same.
Change-Id: I67a5ff3b5fb18c2ce986c5f431f4e41a78fe13a5
Signed-off-by: Taniya Das <tdas@codeaurora.org>
| -rw-r--r-- | drivers/clk/qcom/mmcc-sdm660.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/clk/qcom/mmcc-sdm660.c b/drivers/clk/qcom/mmcc-sdm660.c index 934779f16107..aec73d62bc18 100644 --- a/drivers/clk/qcom/mmcc-sdm660.c +++ b/drivers/clk/qcom/mmcc-sdm660.c @@ -965,8 +965,9 @@ static struct clk_rcg2 dp_pixel_clk_src = { .parent_names = mmcc_parent_names_6, .num_parents = 4, .ops = &clk_dp_ops, + .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, VDD_DIG_FMAX_MAP3( - LOWER, 148380, + LOWER, 154000, LOW, 296740, NOMINAL, 593470), }, |