diff options
| author | Tony Truong <truong@codeaurora.org> | 2017-03-14 12:47:58 -0700 |
|---|---|---|
| committer | Gerrit - the friendly Code Review server <code-review@localhost> | 2017-04-04 17:58:23 -0700 |
| commit | 3fa2736a23dfd0cd80999b2ae2bbe5cbe256d533 (patch) | |
| tree | 913e453bca51e2517e3eb37a7cb36e32948bcb8a | |
| parent | 8f301e1bd16c71f9289f73f98131a8c83197768e (diff) | |
msm: pcie: update mask and linkdown check in PCIe read/write API
The current check for linkdown does not suffice if the default
value of that register is 0xffffffff. PCIe bus driver needs to
also read the device/vendor ID of the client to confirm if it
is really a linkdown. Update the mask method to be compatible
with 64-bit architecture.
Change-Id: Ibe51dff50ff010260a750d73498333ee830fca2c
Signed-off-by: Tony Truong <truong@codeaurora.org>
| -rw-r--r-- | drivers/pci/host/pci-msm.c | 19 |
1 files changed, 12 insertions, 7 deletions
diff --git a/drivers/pci/host/pci-msm.c b/drivers/pci/host/pci-msm.c index 53cb0302cb94..0d50849889d6 100644 --- a/drivers/pci/host/pci-msm.c +++ b/drivers/pci/host/pci-msm.c @@ -3317,7 +3317,7 @@ static inline int msm_pcie_oper_conf(struct pci_bus *bus, u32 devfn, int oper, word_offset = where & ~0x3; byte_offset = where & 0x3; - mask = (~0 >> (8 * (4 - size))) << (8 * byte_offset); + mask = ((u32)~0 >> (8 * (4 - size))) << (8 * byte_offset); if (rc || !dev->enumerated) { config_base = rc ? dev->dm_core : dev->conf; @@ -3352,12 +3352,17 @@ static inline int msm_pcie_oper_conf(struct pci_bus *bus, u32 devfn, int oper, writel_relaxed(wr_val, config_base + word_offset); wmb(); /* ensure config data is written to hardware register */ - if (rd_val == PCIE_LINK_DOWN) - PCIE_ERR(dev, - "Read of RC%d %d:0x%02x + 0x%04x[%d] is all FFs\n", - rc_idx, bus->number, devfn, where, size); - else if (dev->shadow_en) - msm_pcie_save_shadow(dev, word_offset, wr_val, bdf, rc); + if (dev->shadow_en) { + if (rd_val == PCIE_LINK_DOWN && + (readl_relaxed(config_base) == PCIE_LINK_DOWN)) + PCIE_ERR(dev, + "Read of RC%d %d:0x%02x + 0x%04x[%d] is all FFs\n", + rc_idx, bus->number, devfn, + where, size); + else + msm_pcie_save_shadow(dev, word_offset, wr_val, + bdf, rc); + } PCIE_DBG3(dev, "RC%d %d:0x%02x + 0x%04x[%d] <- 0x%08x; rd 0x%08x val 0x%08x\n", |